This invention relates to insulated-gate field-effect transistors, particularly but not exclusively of the vertical power D-MOST type or V-MOST type, having reduced drain series resistance.
The paper entitled "Functional Integration of Power MOS and Bipolar Devices" by J. Tihanyi, International Electron Devices Meeting, 1980, Washington D.C., I.E.E.E. publication CH 1616-2/80/0000-0075, pages 75 to 78, describes several insulated-gate field-effect power transistors comprising a semiconductor body having a surface-adjacent source region of one conductivity type which is surrounded in the body by a surface-adjacent second region of the opposite conductivity type. A third region adjoins the second region and has a lower conductivity-type determining doping concentration. At least a part of said second and third regions is located in a main current path from the source region to a drain of the transistor. A conductive layer is present on an insulating layer on said part of at least the second region to form an insulated gate of the transistor for capacitively controlling in said part a conductive channel in the main current path between the source region and the drain. The principal field-effect transistors described in this paper are of so-called SIPMOS construction which is an ion-implanted variant form of the D-MOST type. It should be noted that the designation MOST is commonly used for insulated-gate field-effect transistors and does not imply that the gate is necessarily a metal nor that the gate insulator is necessarily an oxide. Thus, for example, the described SIPMOS transistors have gates of doped polycrystalline silicon.
Insulated-gate field-effect transistors have advantageous low drive and fast switching characteristics. However, compared with a bipolar power transistor of the same area, an insulated-gate field-effect power transistor has a lower on-conductance (high series resistance) at blocking voltages of about 300 volts and above. This lower on-conductance results from the very high parasitic series resistance of the low-doped (third) region which is associated with the drain of the transistor. Various attempts have been made to combine the low drive and fast switching characteristics of an MOST with the low on-conductance of a bipolar device.
The paper by J. Tihanyi describes various combinations of a SIPMOS transistor and a bipolar device. FIG. 3a of said paper shows one such combination in which (in addition to the previously-mentioned SIPMOS features) a surface-adjacent emitter regin of said one conductivity type is also surrounded in the body by the second region, said emitter region being located at a side of the source region remote from the channel part of the second region and being separated from the source region by an intermediate part of the second region. The source region is electrically connected to said intermediate part. A resistive current path in the second region is present below the emitter region.
The device combination of FIG. 3a of said paper is a lateral MOS-thyristor, the emitter region being a cathode of the thyristor, and an anode region being provided in the low-doped third region. A cathode electrode which contacts the cathode emitter region also contacts the source region and the intermediate part of the second region so as to short-circuit the cathode and source regions to the second region. The cathode-anode path of the thyristor is the main current-carrying path of the combined device, and the MOST is used to trigger the thyristor by supplying its drain current as the firing current to the third region which forms the low-doped n-type base of the thyristor. The forward-biased junction between the anode region and the third region injects minority carriers (holes) which diffuse through the third region to the second region and cause the latching of the device. By thus using the MOST gate as the input of the combined device, only a low input current is needed to switch the structure on. In this manner a bipolar device is given advantageous MOST characteristics.